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ILC7083/ILC7084
150mA SOT-23 Low Noise CMOS RF-LDOTM Regulator
Features
* * * * * * * * * * * Ultra low 1mV dropout per 1mA load 3% output voltage accuracy Only 40VRMS noise Uses low ESR ceramic output capacitor to minimize noise and output ripple Only 100A ground current at 100mA load Ripple rejection up to 85dB at 1kHz, 60dB at 1MHz Excellent line and load transient response Over current / over temperature protection Guaranteed to 150mA output current Industry standard five lead SOT-23 package Fixed 2.5V, 2.7V, 2.85V, 3.0V, 3.3V, 3.6V, 5V output voltage for ILC7083 and adjustable output voltage for ILC7083/ILC7084 Metal mask option available for custom voltages between 2.5V and 5.1V
Description
The ILC7083/ILC7084 is a 150mA low dropout (LDO) voltage regulator designed to provide a high performance solution to low power systems. The device offers a typical combination of low dropout and low quiescent current expected of CMOS parts, while uniquely providing the low noise and high ripple rejection characteristics usually only associated with bipolar LDO regulators. The device has been optimized to meet the needs of modern wireless communications design; Low noise, low dropout, small size, high peak current, high noise immunity. The ILC7083/ILC7084 is designed to make use of low cost ceramic capacitors while outperforming other devices that require tantalum capacitors. As opposed to ILC7084, the ILC7083 has a built in output capacitor discharge circuit active in shutdown mode. This feature is necessary in applications where the output voltage must decrease quickly to zero volt in shutdown mode.
*
Applications
* * * * Cellular phones Wireless communicators PDAs / palmtops / organizers Battery powered portable electronics
Typical Applications
VOUT
5
SOT-23-5
4
COUT
ILC7083
1 2 3
CNOISE
VIN
ON
CIN
OFF
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ILC7083/ILC7084
Pin Assignments
Fixed Voltage Option
GND ON/OFF VIN VIN
1 8
Adjustable Voltage Option
GND ON/OFF
1 8
CNOISE N/C
VOUT
5
CNOISE
4
VOUT
5
VADJ
4
VADJ N/C VOUT VOUT
2
7
2
7
ILC7083-xx
3 6
ILC7083-xx VOUT
1 2 3
ILC7083ADJ or ILC7084ADJ
1 2 3
ILC7083ADJ VIN VIN
3 6
4
5
VOUT
VIN
GND ON/OFF SOT-23-5
VIN
GND ON/OFF SOT-23-5
4
5
SOIC-8
SOIC-8
Pin Description ILC7083-xx (Fixed voltage version)
Pin Number SOIC-8 SOT-23-5 Pin Name 3 and 4 1 2 8 5 and 6 7 1 2 3 4 5 - VIN GND ON/OFF CNOISE VOUT N/C Connect directly to supply Ground pin. Local ground for CNOISE and COUT. By applying less than 0.6V to this pin the device will be turned off. Optional noise bypass capacitor may be connected between this pin and GND. Do not connect CNOISE directly to the main power ground plane. Output Voltage. Connect COUT between this pin and GND. Not Connected Pin Description
Pin Description ILC7083-ADJ (Adjustable voltage version)
Pin Number SOIC-8 SOT-23-5 Pin Name 3 and 4 1 2 8 5 and 6 7 1 2 3 4 5 - VIN GND ON/OFF VADJ VOUT N/C Connect directly to supply Ground pin. Local ground for CNOISE and COUT. By applying less than 0.6V to this pin the device will be turned off. Voltage feedback pin to set the adjustable output voltage. Do not connect a capacitor to this pin. Output Voltage. Connect COUT between this pin and GND. Not Connected Pin Description
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ILC7083/ILC7084
Internal Block Diagram
VIN CNOISE
BANDGAP REFERENCE VREFD ERROR AMPLIFIER TRANSCONDUCTANCE AMPLIFIER
INTERNAL VDD
VOUT
FEEDBACK
GND
ON/OFF
Absolute Maximum Ratings
Parameter Input Voltage On/Off Input Voltage Output Current Output Voltage Package Power Dissipation (SOT-23-5) Maximum Junction Temp Range Storage Temperature Package Thermal Resistance Symbol VIN VON/OFF IOUT VOUT PD TJ(max) TSTG JA Ratings -0.3 to +13.5 -0.3 to VIN Short circuit protected -0.3 to VIN + 0.3 250 (Internally Limited) -40 to +150 -40 to +125 333 Units V mA V mW C C C/W
Recommended Operating Conditions
Parameter Input Voltage Operating Ambient Temperature Min. VOUT + VDO -40 Typ. VOUT + 1 Max. 13 +85 Units V C
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ILC7083/ILC7084
Electrical Characteristics ILC7083/ILC7084
Unless otherwise specified, all limits are at TA=25C; VIN = VOUT(NOM) +1V, IOUT = 1mA, COUT = 1F, VON/OFF = 2V. Boldface type denotes specifications which apply over the specified operating temperature range. Parameter Input Voltage Range Output Voltage Feedback Voltage (ADJ version) Line Regulation Dropout Voltage (Note 3) Symbol VIN VOUT VADJ VOUT/ (VOUT*VIN) VIN - VOUT VOUT(NOM) +1V < VIN < 12V IOUT= 0mA (Note 4) IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 150mA Ground Pin Current IGND IOUT = 0mA IOUT = 10mA IOUT = 50mA IOUT = 100mA IOUT = 150mA Shutdown (OFF) Current ON/OFF Input Voltage ON/OFF Pin Input Current Peak Output Current (Note 4) Output Noise Voltage (RMS) ION/OFF VON/OFF IIN( ON/OFF) IOUT(peak) eN VON/OFF = 0V High = Regulator On Low = Regulator Off VON/OFF = 0.6V, regulator OFF VON/OFF = 2V, regulator ON VOUT > 0.95VOUT(NOM), tpw = 2ms BW = 300Hz to 50kHz, CIN = 1F CNOISE = 0.01F, COUT = 2.2F, IOUT = 10mA Freq. = 1kHz COUT = 4.7F, IOUT = 100mA Freq. = 10kHz Freq. = 1MHz VIN: VOUT(NOM) + 1V to VOUT(NOM) + 2V, tr/tf = 2s; IOUT = 150mA IOUT: 1mA to 150mA; tr < 5S VOUT = 0V Conditions 1mA < IOUT < 150mA 1mA < IOUT < 150mA Min 2 -3 -4 1.217 1.204 Typ VOUT(NOM) VOUT(NOM) 1.255 0.007 0.1 10 50 100 150 95 100 100 100 115 0.1 1.5 0.6 0.3 1 500 40 A mA VRMS Max 13 +3 +4 1.292 1.305 0.014 0.032 1 2 25 35 75 100 150 200 225 300 200 220 220 240 220 240 240 260 260 280 2 Units V %VOUT (NOM) V %/V mV
A
A
400
Ripple Rejection
VOUT/VIN
Dynamic Line Regulation
VOUT(line)
85 70 60 14
dB
mV
Dynamic Load Regulation Short Circuit Current
VOUT(load) ISC
40 600
mV mA
Notes: 1. Absolute maximum ratings indicate limits which when exceeded may result in damage to the component. Electrical specifications do not apply when operating the device outside of its rated operating conditions. 2. Specified Min/Max limits are production tested or guaranteed through correlation based on statistical control methods. Measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing. 3. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the nominal value measured with an IV differential. 4. Guaranteed by design.
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ILC7083/ILC7084
Operation
The ILC7083/ILC7084 LDO design is based on an advanced circuit configuration for which patent protection has been applied. Typically it is very difficult to drive a capacitive output with an amplifier. The output capacitance produces a pole in the feedback path, which upsets the carefully tailored dominant pole of the internal amplifier. Traditionally the pole of the output capacitor has been "eliminated" by reducing the output impedance of the regulator such that the pole of the output capacitor is moved well beyond the gain bandwidth product of the regulator. In practice, this is difficult to do and still maintain high frequency operation. Typically the output impedance of the regulator is not simply resistive, such that the reactive output impedance interacts with the reactive impedance of the load resistance and capacitance. In addition, it is necessary to place the dominant pole of the circuit at a sufficiently low frequency such that the gain of the regulator has fallen below unity before any of the complex interactions between the output and the load occur. The ILC7083/ILC7084 does not try to eliminate the output pole, but incorporates it into the stability scheme. The load and output capacitor forms a pole, which rolls off the gain of the regulator below unity. In order to do this the output impedance of the regulator must be high, looking like a current source. The output stage of the regulator becomes a transconductance amplifier, which converts a voltage to a current with a substantial output impedance. The circuit which drives the transconductance amplifier is the error amplifier, which compares the regulator output to the band gap reference and produces an error voltage as the input to the transconductance amplifier. The error amplifier has a dominant pole at low frequency and a "zero" which cancels out the effects of the pole. The zero allows the regulator to have gain out to the frequency where the output pole continues to reduce the gain to unity. The configuration of the poles and zero are shown in Figure 1. Instead of powering the critical circuits from the unregulated input voltage, the CMOS RF LDO powers the internal circuits such as the bandgap, the error amplifier and most of the transconductance amplifier from the boot strapped regulated output voltage of the regulator. This technique offers extremely high ripple rejection and excellent line transient response.
DOMINANT POLE 85 dB
GAIN
OUTPUT POLE
COMPENSATING ZERO
UNITY GAIN
FREQUENCY
Figure 1. ILC7083/ILC7084 RF LDO Frequency Response
A block diagram of the regulator circuit used in the ILC7083 is shown in Figure 2, which shows the input-to-output isolation and the cascaded sequence of amplifiers that implement the pole-zero scheme outlined above. The ILC7083/ILC7084 is designed in a CMOS process with some minor additions, which allow the circuit to be used at input voltages up to 13V. The resulting circuit exceeds the frequency response of traditional bipolar circuits. The ILC7083/ILC7084 is very tolerant of output load conditions with the inclusion of both short circuit and thermal overload protection. The device has a very low dropout voltage, typically a linear response of 1mV per milliamp of load current, and none of the quasi-saturation characteristics of a bipolar output devices. All the good features of the frequency response and regulation are valid right to the point where the regulator goes out of regulation in a 4 millivolt transition region. Because there is no base drive, the regulator is capable of providing high current surges while remaining in regulation. This is shown in the high peak current of 500mA which allows for the ILC7083/ILC7084 to be used in systems that require short burst mode operation.
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ILC7083/ILC7084
VIN CNOISE
BANDGAP REFERENCE VREFD ERROR AMPLIFIER
INTERNAL VDD
TRANSCONDUCTANCE AMPLIFIER
VOUT
FEEDBACK
GND
ON/OFF
Figure 2. ILC7083 RF LDO Regulator Block Diagram
Shutdown (ON/OFF) Operation
The ILC7083/ILC7084 output can be turned off by applying 0.6V or less to the device's ON/OFF pin (pin 3). In shutdown mode, the ILC7083/ILC7084 draws less than 1A quiescent current. In shutdown mode the output of ILC7083 is coupled to a low impedance circuit which discharges the output capacitor. The output of the ILC7083/ILC7084 is enabled by applying 1.5V to 13V at the ON/OFF pin. In applications where the ILC7083 output will always remain enabled, the ON/OFF pin may be connected to VIN (pin 1). The ILC7083/ ILC7084's shutdown circuitry includes hysteresis, as such the device will operate properly even if a slow moving signal is applied to the ON/OFF pin.
In normal operation, the die temperature should be limited to under 150C.
Adjustable Output Voltage
Figure 5 shows how an adjustable output voltage can be easily achieved using ILC7083/ILC7084-ADJ. The output voltage, VOUT is given by the following equation: VOUT = 1.255V x (R1/R2 + 1)
R1 VOUT R2
5 SOT23-5 4 VADJ
ILC7083-ADJ or ILC7084-ADJ
Short Circuit Protection
The ILC7083/ILC7084 output can withstand momentary short circuit to ground. Moreover, the regulator can deliver very high output peak current due to its 1A instantaneous short circuit current capability.
COUT VIN CIN
1
2
3 ON OFF
Thermal Protection
The ILC7083/ILC7084 also includes a thermal protection circuit which shuts down the regulator when die temperature exceeds 150C due to overheating. In thermal shutdown, once the die temperature cools to below 140C, the regulator is enabled. If the die temperature is excessive due to high package power dissipation, the regulator's thermal circuit will continue to pulse the regulator on and off. This is called thermal cycling. Excessively high die temperature may occur due to high differential voltage across the regulator or high load current or high ambient temperature or a combination of all three. Thermal protection protects the regulator from such fault conditions and is a necessary requirement in today's designs. 6
Figure 3. Application Circuit for Adjustable Output Voltage
For best results, a resistor value of 470k or less may be used for R2. The output voltage can be programmed from 2.5V to 12V. Note that an external capacitor should not be connected to the adjustable feedback pin (pin 4). Connecting an external capacitor to pin 4 may cause regulator instability and lead to oscillations.
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ILC7083/ILC7084
Maximum Output Current
The maximum output current available from the ILC7083/ ILC7084 is limited by the maximum package power dissipation as well as the device's internal current limit. For a given ambient temperature, TA, the maximum package power dissipation is given by: PD(MAX) = (TJ(MAX) - TA) / JA where TJ(MAX) = 150C is the maximum junction temperature and JA = 333C/W is the package thermal resistance. For example at TA = 85C ambient temperature, the maximum package power dissipation is; PD(MAX) = 195mW. The maximum output current can be calculated from the following equation: IOUT(MAX) < PD(MAX) / (VIN - VOUT) For example at VIN = 6V, VOUT = 5V and TA = 85C, the maximum output current is IOUT(MAX) < 195mA. At higher output current, the die temperature will rise and cause the thermal protection circuit to be enabled.
the regulator may be damaged. This condition must be avoided. In many applications a large value input capacitor, CIN, will hold VIN higher than VOUT and decay slower than VOUT when the LDO is powered off.
Output Capacitor Selection
Fairchild strongly recommends the use of low ESR (equivalent series resistance) ceramic capacitors for COUT and CNOISE. The ILC7083/ILC7084 is stable with low ESR capacitor (as low as zero ). The value of the output capacitor should be 1F or higher. Either ceramic chip or a tantalum capacitor may be used at the output. Use of ceramic chip capacitors offer significant advantages over tantalum capacitors. A ceramic capacitor is typically cheaper than a tantalum capacitor, it usually has a smaller footprint, lower height, and lighter weight than a tantalum capacitor. Furthermore, unlike tantalum capacitors which are polarized and can be damaged if connected incorrectly, ceramic capacitors are non-polarized. Low value ceramic chip capacitors with X5R or X7R dielectric are available in the 100pF to 4.7F range. Beware of using ceramic capacitors with Y5V dielectric since their ESR increases significantly at cold temperatures. Please see the table of recommended ceramic capacitors for use at the output of ILC7083/ILC7084. Note: If a tantalum output capacitor is used then for stable operation. We recommend a low ESR tantalum capacitor with maximum rated ESR at or below 0.4. Low ESR tantalum capacitors, such as the TPS series from AVX Corporation (www.avxcorp.com) or the T495 series from Kemet (www.kemet.com) may be used. In applications where a high output surge current can be expected, use a high value but low ESR output capacitor for superior load transient response. The ILC7083/ILC7084 is stable with no load.
Application Hints
Figure 4 shows the typical application circuit for the ILC7083.
VOUT 5 SOT23-5 4 COUT VIN CIN 1
ILC7083
CNOISE
2
3 ON OFF
Noise Bypass Capacitor
In low noise applications, the self noise of the ILC7083 can be decreased further by connecting a capacitor from the noise bypass pin (pin 4) to ground (pin 2). The noise bypass pin is a high impedance node as such care should be taken in printed circuit board layout to avoid noise pick-up from external sources. Moreover, the noise bypass capacitor should have low leakage. Noise bypass capacitors with a value as low as 470pF may be used. However, for optimum performance, use a 0.01F or larger, ceramic chip capacitor. Note that the turn on and turn off response of the ILC7083 is inversely proportional to the value of the noise bypass capacitor. For fast turn on and turn off, use a small value noise bypass capacitor. In applications where exceptionally low output noise is not required, consider omitting the noise bypass capacitor altogether.
Figure 4. Basic Application Circuit for Fixed Output Voltage Versions
Input Capacitor
An input capacitor CIN of value 1F or larger should be connected from VIN to the main ground plane. This will help to filter supply noise from entering the LDO. The input capacitor should be connected as close to the LDO regulator input pin as is practical. Using a high-value input capacitor will offer superior line transient response as well as better power supply ripple rejection. A ceramic or tantalum capacitor may be used at the input of the LDO regulator. Note that there is a parasitic diode from the LDO regulator output to the input. If the input voltage swings below the regulator's output voltage by a couple of hundred millivolts then
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ILC7083/ILC7084
The Effects of ESR (Equivalent Series Resistance)
The ESR of a capacitor is a measure of the resistance due to the leads and the internal connections of the component. Typically measured in m (milli-ohms) it can increase to ohms in some cases. Wherever there is a combination of resistance and current, voltages will be present. The control functions of LDOs use two voltages in order to maintain the output precisely; VOUT and VREF. With reference to the block diagram in Figure 4, VOUT is fed back to the error amplifier and is used as the supply voltage for the internal components of the ILC7083/ILC7084. So any change in VOUT will cause the error amplifier to try to compensate to maintain VOUT at the set level and noise on VOUT will be reflected into the supply of each internal components of the ILC7083/ILC7084. So any change in VOUT will cause the error amplifier to try to compensate to maintain VOUT at the set level and noise on VOUT will be reflected into the supply of each internal circuit. The reference voltage, VREF, is influenced by the CNOISE pin. Noise into this pin will add to the reference voltage and be fed through the circuit. These factors will not cause a problem if some simple steps are taken. Figure 5 shows where these added ESR resistances are present in the typical LDO circuit.
VOUT IOUT
these resistances may be very small, but a summation of several currents can develop detectable voltage ripple and will be amplified by the LDO. Particularly the accumulation of current flows in the ground plane can develop significant voltages unless care is taken. With a degree of care, the ILC7083/ILC7084 will yield outstanding performance.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full advantage of any high performance LDO regulator requires paying careful attention to grounding and printed circuit board (PCB) layout.
VOUT IOUT
ESR
RPCB RPCB
I1 COUT
ESR CNOISE
5 SOT-23-5 4
ILC7083
VIN CIN
RPCB
1
2
RPCB
3 ON OFF
Figure 6. Inherent PCB resistance
R*
IC COUT RC
Figure 7 shows the effects of poor grounding and PCB layout magnified by the ESR and PCB resistances and the accumulation of current flows. Note that particularly during high output load current, the LDO regulator's ground pin and the ground return for COUT and CNOISE are not at the same potential as the system ground. This is due to high frequency impedance caused by PCB's trace inductance and DC resistance. The current loop between COUT, CNOISE and the LDO regulator's ground pin will degrade performance of the LDO. Figure 8 shows an optimum schematic. In this schematic, high output surge current has little effect on the ground current and noise bypass current return of the LDO regulator. Note that the key difference here is that COUT and CNOISE are directly connected to the LDO regulator's ground pin. The LDO is then separately connected to the main ground plane and returned to a single point system ground. The layout of the LDO and its external components are also based on some simple rules to minimize EMI and output voltage ripple.
5 SOT-23-5 4
ILC7083
CNOISE
VIN
1 R*
2
RF LDOTM Regulator
3 ON OFF
CIN
Figure 5. ESR Present in COUT and CNOISE
With this in mind low ESR components will offer better performance where the LDO may be subjected to large load transients current. ESR is less of a problem with CIN as the voltage fluctuations at the input will be filtered by the LDO. However, being aware of these current flows, there is also another potential source of induced voltage noise from the resistance inherent in the PCB trace. Figure 6 shows where the additive resistance of the PCB can manifest itself. Again
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ILC7083/ILC7084
VOUT
5
4
CNOISE
ILC7083
SOT-23-5
COUT
C IN
GND2
GND
ON/OFF
CNOISE
VIN
1
2
3
ICOUT
True GND (0V)
I LOAD +IC OUT +IC NOISE +IGND
GND1 I LOAD +IC OUT +IC NOISE
GND3
GND4 GND5 I LOAD I LOAD +IC OUT
Figure 7. Effects of Poor Circuit Layout
VOUT C NOISE
5 4
ILC7083
SOT-23-5
VIN VBATT + GND
DC/DC Converter
1
2
3 ON/OFF
ESR<0.5
CIN
Local Ground
Ground Plane
Ground Plane
Ground Plane
Ground Plane
Figure 8. Recommended Application Circuit Schematic
Fairchild Semiconductor - Eval. Board
Figure 9. Recommended Application Circuit Layout (not drawn to scale) Note, ground plane is bottom layer of PCB and connects to top layer ground connections through vias.
LOAD
C OUT
LOAD
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ILC7083/ILC7084
Evaluation Board Parts List (for Figure 9)
Label U1 J1 Cin Cnoise Cout Part Number ILC7083AIM5-30 69190-405 GRM40 Y5V 105Z16 ECU-V1H103KBV GRM42-6X5R475K10 Manufacturer Berg muRata Panasonic muRata Description Connector, four position header Ceramic capacitor, 1F,16V, SMT (size 0805) Ceramic capacitor, 0.01F,16V, SMT (size 0603) Ceramic capacitor, 4.7F,16V, SMT (size 1206) Fairchild Semiconductor 150mA RF LDOTM regulator
Grounding Recommendations
1. 2. Connect CIN between VIN of the ILC7083 and the "GROUND PLANE". Keep the ground side of COUT and CNOISE connected to the "LOCAL GROUND" and not directly to the "GROUND PLANE". On multilayer boards use component side copper for grounding around the ILC7083 and connect back to a "GROUND PLANE" using vias. If using a DC-DC converter in your design, use a star grounding system with separate traces for the power ground and the control signals. The star should radiate from where the power supply enters the PCB.
Layout Considerations
1. Place all RF LDO related components; ILC7083, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT as close together as possible. Keep the output capacitor COUT as close to the ILC7083 as possible with very short traces to the VOUT and GND pins. The traces for the related components; ILC7083, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT can be run with minimum trace widths close to the LDO. Maintain a separate "LOCAL GROUND" remote from the "GROUND PLANE" to ensure a quiet ground near the LDO.
2.
3.
3.
4.
4.
Figure 9 shows how this circuit can be translated into a PCB layout.
Recommended Ceramic Output Capacitors
COUT 1F Capacitor Size 0805 0805 0805 1206 1206 1206 2.2F 0805 0805 1206 4.7F 1206 1206 0 to 150mA 0 to 150mA IOUT 0 to 150mA Dielectric X5R X7R X7R X7R X7R X5R X5R X5R X5R X5R X7R Part Number C2012X5R1A105KT GRM40X7R105K010 LMK212BJ105KG GRM42-6X7R105K016 EMK316BJ105KL TMK316BJ105KL GRM40X5R225K 6.3 C2012X5R0J225KT EMK316BJ225ML GRM42-6X5R475K010 LMK316BJ475ML Capacitor Vendor TDK muRata Taiyo-Yuden muRata Taiyo-Yuden Taiyo-Yuden muRata TDK Taiyo-Yuden muRata Taiyo-Yuden
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ILC7083/ILC7084
Typical Performance Characteristics ILC7083/ILC7084
Unless otherwise specified: TA = 25C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Output Voltage vs Temperature
3.015 3.01 3.4
Dropout Characteristics VOUT = 3.3V COUT = 1F (Ceramic) IOUT = 0mA IOUT = 10mA IOUT = 50mA
VOUT = 3.0V COUT = 1F (Ceramic)
3.3
Output voltage (V)
VOUT (V)
3.005 3 2.995 2.99 2.985 -50
3.2
3.1
IOUT = 100mA IOUT = 150mA
3 0 50 100 150 3 3.2 3.4 3.6
Temperature (C) Dropout Voltage vs Temperature
250 250
VIN (V) Dropout Voltage vs IOUT VOUT = 3.0V Dropout voltage (mV)
200
VOUT = 3.0V Dropout voltage (mV)
200
IOUT = 150mA
TA = 85C TA = 25C
150
IOUT = 100mA
150
100
IOUT = 50mA
100
TA = -40C
50
50
IOUT = 0mA
0 -40 25 85 0 0 50 100 150
Temperature (C) Ground Current vs Input Voltage
150 6
Output Current (mA) Line Transient Response VIN: tr/tf < 1 s VOUT = 3.0V COUT = 2.2 F (Ceramic) IOUT = 100 mA
4
VOUT = 3.0 V IOUT = 10mA COUT = 1F (Ceramic) IOUT = 50mA 125 IOUT = 150mA IGND (A) IOUT = 0mA
100
VIN (V) VOUT (V)
12 14
5
3.01 3.00 2.99 2.98
75
IOUT = 100mA
50 2 4 6 8 10
5s/div
VIN (V)
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ILC7083/ILC7084
Typical Performance Characteristics ILC7083/ILC7084
Unless otherwise specified: TA = 25C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Load Transient Response
3.15
Short Circuit Current VIN = 4V
Output Shorted to Gnd 1.5 at time, t = 0 1.0 Thermal Cycling
VOUT (V)
3.10 3.05 3.00 2.95
VOUT = 3.0V COUT = 1 F || 0.47 F (Ceramic)
ISC (A) 100s/div
IOUT (mA)
0.5
100 0 1
t=0
5ms/div
On/Off Transient Response VON/OFF (V)
VOUT = 2.8V IOUT = 10mA COUT = 1F
On/Off Transient Response VON/OFF (V)
15 10 5 0 3 VOUT = 2.8V IOUT = 150mA Without CNOISE Capacitor COUT = 1F
15 10 5 0 3 Without CNOISE Capacitor
VOUT (V)
1 0
VOUT (V) 100S/div On/Off Transient Response
2
2 1 0
100S/div On/Off Transient Response VON/OFF (V)
15 10 5 0 3 VOUT = 2.8V IOUT = 150mA CNOISE = 0.01F, COUT = 1F
VON/OFF (V)
15 10 5 0 3 VOUT = 2.8V IOUT = 10mA CNOISE = 0.01F, COUT = 1F
VOUT (V)
VOUT (V) 5mS/div
2 1 0
2 1 0
5mS/div
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Typical Performance Characteristics ILC7083/ILC7084
Unless otherwise specified: TA = 25C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Spectral Noise Density
10 VOUT = 2.8V IOUT = 50mA CNOISE = 0.01F COUT = 1F (Ceramic) 0.1 10
Spectral Noise Density
VOUT = 2.8V COUT = 2.2F CNOISE = 0.01F
Noise (V/Rt Hz)
1
Noise (V/Rt Hz)
1
IOUT = 50mA, 100mA or 150 mA 0.1
0.01
COUT = 2.2F or 4.7F (Ceramic) COUT = 10F (Ceramic)
0.01
IOUT = 1 mA
0.001 10 100 1K 10K 100K 1M 10M
0.001 10 100 1K 10K 100K 1M
Frequency (Hz)
Frequency (Hz)
Output Noise Voltage vs. CNOISE
90 80 70 CNOISE = 1.2nF 5.6nF 8.2nF 0.039F 0.047F 0.022F 0.01F VOUT = 3V IOUT = 10mA COUT = 2.2F(Ceramic) 90 80 70
Output Noise Voltage vs. CNOISE
CNOISE = 1.2nF VOUT = 3V IOUT = 10mA COUT = 4.7F(Ceramic)
Noise (Vrms)
60 50 40 30 20 10 0
Noise (Vrms)
60 50 40 30 20 10 0
5.6nF 8.2nF 0.039F 0.047F 0.022F 0.016F
100 Hz- 50 KHz
100 Hz- 100 KHz
300 Hz- 50 KHz
300 Hz- 100 KHz
100 Hz- 50 KHz
100 Hz- 100 KHz
300 Hz- 50 KHz
300 Hz- 100 KHz
Freq Band Ripple Rejection vs. Frequency
120 80
Freq Band Ripple Rejection vs. Frequency Ripple Rejection (dB)
VOUT = 2.8V IOUT = 150mA COUT = 4.7F
Ripple Rejection (dB)
100 80 60 40 20 0 10
VOUT = 3V IOUT = 10mA COUT = 4.7F COUT = 10F
70 60 50 40 30
COUT = 2.2F
COUT = 1F COUT = 2.2F
COUT = 1F 20 10 0 10 100 1K 10K 100K
COUT = 10F
100
1K
10K
100K
1M
10M
1M
10M
Frequency (Hz)
Frequency (Hz)
REV. 1.0.9 1/28/03
13
ILC7083/ILC7084
Mechanical Dimensions
8-Lead Plastic Surface Mount (SOIC)
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .0075 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C
h x 45 C
e
L
14
REV. 1.0.9 1/28/03
ILC7083/ILC7084
5-Lead Plastic Surface Mount (SOT-23-5)
Symbol A A1 B c D E e e1 H L Inches Min. .035 .000 .008 .003 .106 .059 Max. .057 .006 .020 .010 .122 .071 Millimeters Min. .90 .00 .20 .08 2.70 1.50 Max. 1.45 .15 .50 .25 3.10 1.80 Notes: Notes 1. Package outline exclusive of mold flash & metal burr. 2. Package outline exclusive of solder plating. 3. EIAJ Ref Number SC-74A.
.037 BSC .075 BSC .087 .126 .004 .024 0 10
.95 BSC 1.90 BSC 2.20 3.20 .10 .60 0 10
B
e L
E
H
e1 D
c
A
A1
REV. 1.0.9 1/28/03
15
ILC7083/ILC7084
Ordering Information (TA = -40C to +85C)
Part Number ILC7083AIM525X ILC7083AIM527X ILC7083AIM5285X ILC7083AIM530X ILC7083AIM533X ILC7083AIM536X ILC7083AIM550X ILC7083AIM5ADJX ILC7083AIK30X ILC7083AIKADJ ILC7084AIM5ADJX Output Voltage (V) 2.5 2.7 2.85 3.0 3.3 3.6 5.0 Adjustable 3.0 Adjustable Adjustable Package SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOIC-8 SOIC-8 SOT-23-5 Package Marking BM BN BJ BB BC BD BE BF 7083A1K3 7083A1K DF
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 1/28/03 0.0m 001 Stock#DS30007083 2003 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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